Title :
An efficient asynchronous multiplier
Author :
Goodman, Rodney M. ; Mcauley, Anthony J.
Author_Institution :
Dept. of Electr. Eng., California Inst. of Technol., Pasadena, CA, USA
Abstract :
An efficient asynchronous serial-parallel multiplier architecture is presented. If offers significant advantages over conventional clocked versions, without some of the drawbacks normally associated with similar asynchronous techniques, such as excessive area. It is shown how a general asynchronous communication element can be designed and illustrated with the CMOS multiplier chip implementation. It is also shown how the multiplier could form the basis for a faster and more robust implementation of the Rivest-Sharmir-Adleman (RSA) public-key cryptosystem
Keywords :
CMOS integrated circuits; multiplying circuits; CMOS multiplier chip implementation; RSA public key cryptosystem; asynchronous communication element; asynchronous serial-parallel multiplier architecture; Asynchronous communication; Authentication; Clocks; Communication system security; Hardware; Heart; Power system security; Public key cryptography; Robustness; Systolic arrays;
Conference_Titel :
Systolic Arrays, 1988., Proceedings of the International Conference on
Conference_Location :
San Diego, CA
Print_ISBN :
0-8186-8860-2
DOI :
10.1109/ARRAYS.1988.18096
