Title :
A logic synthesis system for VHDL design descriptions
Author :
Dillinger, T.E. ; McCarthy, K.M. ; Mosher, T.A. ; Neumann, D.R. ; Schmidt, R.A.
Author_Institution :
IBM Application Bus. Syst., Rochester, MN, USA
Abstract :
The VHSIC hardware description language (VHDL) is emerging as an industry standard for the modeling of electronic systems. A description is given of a logic synthesis system developed to realize ASIC CMOS chip designs from VHDL descriptions, designs optimized for cell count and performance. The utilization of VHDL attributes and the interpretation of attribute data by synthesis transformations are highlighted. Timing optimization algorithms based upon calculated timing slack values are described in detail. The unique means by which clock repowering trees are incorporated is also discussed.<>
Keywords :
CMOS integrated circuits; logic CAD; specification languages; ASIC CMOS chip designs; VHDL attributes; VHDL design descriptions; VHSIC hardware description language; attribute data interpretation; calculated timing slack values; cell count; clock repowering trees; electronic systems modelling; industry standard; logic synthesis system; performance; synthesis transformations; timing optimization algorithms; Application specific integrated circuits; CMOS logic circuits; Chip scale packaging; Design optimization; Electronics industry; Hardware design languages; Logic design; Semiconductor device modeling; Timing; Very high speed integrated circuits;
Conference_Titel :
Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-1986-4
DOI :
10.1109/ICCAD.1989.76906
