Title :
Two-terminal transistor memory cell using breakdown
Author_Institution :
Bell Telephone Labs., Inc., Murray Hill, NJ, USA
Abstract :
A transient charge storage memory cell utilizing a two-terminal transistor structure and junction breakdown will be described, illustrated by a simple fabrication scheme that avoids breakdown degradation. Experimental measurements on such cells will be offered.
Keywords :
Degradation; Electric breakdown; Fabrication; High speed integrated circuits; Parasitic capacitance; Silicon; Telephony;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1971 IEEE International
Conference_Location :
Philadelphia, PA, USA
DOI :
10.1109/ISSCC.1971.1154948
