DocumentCode :
2851596
Title :
Exploiting RAM for fault-tolerant functions in FPGA
Author :
Frigerio, Laura ; Salice, Fabio
Author_Institution :
Politecnico di Milano, Milan
fYear :
2007
fDate :
16-18 Dec. 2007
Firstpage :
145
Lastpage :
150
Abstract :
When realizing a reliable digital system, special attention has to be paid if the target device is an FPGA. In this case, classical fault tolerance techniques are usually not suited to protect the design. This is due to the actual resources used to implement the design, that involves sequential elements even for the combinatorial function and routing. In this paper a method to protect generic functions in FPGA is presented, taking advantage of embedded synchronous memories available on modern FPGAs. As a case study, the implementation of some common functions is proposed along with some optimizations to reduce the use of resources.
Keywords :
circuit optimisation; embedded systems; fault tolerance; field programmable gate arrays; logic testing; random-access storage; FPGA; RAM; circuit optimization; embedded synchronous memories; fault-tolerant functions; field programmable gate arrays; random-access storage; Circuit faults; Fault tolerance; Field programmable gate arrays; Logic devices; Protection; Random access memory; Read-write memory; Redundancy; Routing; Single event upset;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design and Test Workshop, 2007. IDT 2007. 2nd International
Conference_Location :
Cairo
Print_ISBN :
978-1-4244-1824-4
Electronic_ISBN :
978-1-4244-1825-1
Type :
conf
DOI :
10.1109/IDT.2007.4437448
Filename :
4437448
Link To Document :
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