Power Grid Automatic Metal Filling Algorithm Forming Maximum on-chip Decoupling Capacitance

With the extensive scaling in transistor sizes, more functionality has gone on single chip. Modern mixed signal chips designers face problems regarding the supply noise due to the simultaneous switching noise (SSN). SSN is enforced on power supply grid due to switching digital circuits. Supply SSN has a deep impact on nearby analog circuits performance. The need for supply decoupling capacitance by analog circuits is essential. MOS Decoupling capacitance are prone to process and temperature variations. In this paper, we present an algorithm for generating power distribution grid with maximum parasitic capacitance for power supply decoupling using free metal layers. The automatically generated layout is DRC free. The algorithm has been tested on 0.13 mum generic process producing 6.01 pF for bottom plate capacitance and 2.34 pF for side wall capacitance with a total capacitance of 8.35 pF on 0.5 mm times 0.5 mm of chip area.