Digital VLSI multiprocessor design for neurocomputers

Author

Chang, Chia-Fen ; Sheu, Bing J.

Author_Institution

Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA

Volume

2

fYear

1992

fDate

7-11 Jun 1992

Firstpage

1

Abstract

The architecture and circuit design of digital processors for general-purpose neurocomputing are presented. The processing element is suitable for a tightly coupled multiprocessor chip connected in one-dimensional ring or two-dimensional mesh fashion. An off-chip microprogrammed array controller broadcasts instructions to all processing elements. Mappings of the feedforward and feedback operations in the backpropagation neural network into the mesh-connected processing element matrix are described. Detailed design of the circuit blocks is also described. More than 128 processing elements can be implemented in a super chip by use of advanced 0.5-μm CMOS technology to achieve 2.56 billion operations per second

Keywords

VLSI; multiprocessing systems; neural chips; VLSI multiprocessor design; backpropagation neural network; feedback; feedforward; neurocomputers; CMOS technology; Circuit synthesis; Computer architecture; Coupling circuits; Image processing; Neural engineering; Neural networks; Neurons; Signal processing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Neural Networks, 1992. IJCNN., International Joint Conference on

Conference_Location

Baltimore, MD

Print_ISBN

0-7803-0559-0

Type

conf

DOI

10.1109/IJCNN.1992.226993

Filename

226993