DocumentCode :
2851776
Title :
System Level Power and Energy Modeling for Signal Processing Applications
Author :
KTARI, Jalel ; Abid, Mohamed
Author_Institution :
CES Nat. Eng., Sfax
fYear :
2007
fDate :
16-18 Dec. 2007
Firstpage :
218
Lastpage :
221
Abstract :
This article presents a new methodology of consumption and performance characterization of software´s intellectual property (IPs) computing on DSPs. These IPs are generally submitted to various constraints especially the real time and energy. The proposed approach exploits parametric models representing the consumption´s behavior of both DSP´s architecture and algorithm. High-level parametric laws of consumption and performance are established. This methodology permits to deduce the energy and the adequate configuration of many applications written in an advanced language (Strict ANSI-C) for a given target. The approach is proved using signal processing applications: Fast Fourier Transform and Finite Impulse Response filter running on C6710 and C5510.
Keywords :
digital signal processing chips; embedded systems; low-power electronics; energy modeling; fast Fourier transform; finite impulse response filter; intellectual property; signal processing applications; system level power modeling; Application software; Computer architecture; Digital signal processing; Fast Fourier transforms; Intellectual property; Parametric statistics; Power system modeling; Signal processing; Signal processing algorithms; Software performance; DSP; Low power; MPEG2; Modeling; methodology;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design and Test Workshop, 2007. IDT 2007. 2nd International
Conference_Location :
Cairo
Print_ISBN :
978-1-4244-1824-4
Electronic_ISBN :
978-1-4244-1825-1
Type :
conf
DOI :
10.1109/IDT.2007.4437463
Filename :
4437463
Link To Document :
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