Title :
Computer-generated IGFET layout using a vertically-packed weinberger arrangement
Author_Institution :
Bell Telephone Labs., Inc., Murray Hill, NJ, USA
Abstract :
A program which vertically packs IGFET logic circuit nodes in the modular Weinberger arrangement will be discussed. Program output can interface directly with artwork generators. Area savings of up to 50% have been obtained.
Keywords :
Computer errors; Counting circuits; Delay; Fabrication; Laboratories; Large scale integration; Layout; Logic circuits; Telephony; Wire;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1971 IEEE International
Conference_Location :
Philadelphia, PA, USA
DOI :
10.1109/ISSCC.1971.1154959
