DocumentCode
2851877
Title
A 50MS/s 80dB SFDR digital calibrated pipelined ADC with workload-balanced MDAC
Author
Qin, Yajie ; Chen, Qihui ; Signed, S. ; Hong, Zhiliang
Author_Institution
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
fYear
2011
fDate
17-18 Nov. 2011
Firstpage
1
Lastpage
2
Abstract
A workload-balanced multiplying digital-to-analog converter (WB-MDAC) is proposed to improve the settling efficiency of multi-bit pipeline stages, and demonstrated in a 14-bit 50-MS/s digital calibrated pipelined ADC. The presented ADC occupies an active area of 1.3 mm2 in 0.13-μm 1P8M CMOS technology, including internal reference buffers. It dissipates 76mW from a 1.2-V supply, and achieves 64.4 dB SNDR and over 80 dB SFDR.
Keywords
CMOS integrated circuits; analogue-digital conversion; digital-analogue conversion; 1P8M CMOS technology; SFDR digital calibrated pipelined ADC; internal reference buffers; multibit pipeline stages; power 76 mW; size 0.13 mum; voltage 1.2 V; workload-balanced MDAC; workload-balanced multiplying digital-to-analog converter; CMOS integrated circuits; Calibration; Capacitors; Gain; Prototypes; Solid state circuits; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices and Solid-State Circuits (EDSSC), 2011 International Conference of
Conference_Location
Tianjin
ISSN
Pending
Print_ISBN
978-1-4577-1998-1
Electronic_ISBN
Pending
Type
conf
DOI
10.1109/EDSSC.2011.6117737
Filename
6117737
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