Title :
An accurate timing model for fault simulation in MOS circuits
Author :
Kim, S. ; Banerjee, P.
Author_Institution :
Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
Abstract :
An accurate timing model is presented for MOS circuits, which is based on a multiple-valued logic representation, accurate RC models for delay calculations derived from transistor characteristics and slope information, and accurate models for physical failures. A delay fault simulator (FACT) based on this model has been implemented. Results for various MOS circuits are described and compared with those for SPICE and RSIM.<>
Keywords :
MOS integrated circuits; circuit analysis computing; fault location; logic testing; FACT; MOS circuits; RSIM; SPICE; accurate RC models; accurate timing model; delay calculations; delay fault simulator; fault simulation; multiple-valued logic representation; physical failures; slope information; transistor characteristics; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Delay; Logic circuits; MOSFETs; Timing; Very large scale integration; Voltage;
Conference_Titel :
Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-1986-4
DOI :
10.1109/ICCAD.1989.76908
