Post-Fabrication Clock-Timing Adjustment for Digital LSIs Ensuring Operational Timing Margins

To solve the problem of fluctuations in clock timing with digital LSIs (also known as the "clock skew" problem), we propose a genetic algorithm (GA) based clock adjustment method that ensures robust clock-timing to cope with fluctuations in the LSI environment such as temperature or power supply voltage. This method is realized by the combination of dedicated adjustable circuitry and adjustment GA software, with the values for multiple adjustable delay circuits inserted into the clock lines being determined by the GA software after fabrication. Experimental results demonstrate that the proposed method can enhance the operational yields of developed test chips while ensuring sufficient timing margins.