Automatic mixed-signal design verification instrumentation with observation specification language

A rigorous approach for quantifying the completeness of design verification for mixed-signal circuits is proposed. A metric, Enclosure, is proposed. A methodology for its measurement is described, using Verilog-A wrappers and commercial simulators to capture observation data in an XML format. A prototype observation specification language is used as a simple description to specify the contents of verification wrappers or instrumentation modules, allowing the necessary automation. A tool to build the instrumentation modules from this description is developed in perl. Using a CML-Buffer circuit as an example, the resulting data is presented in a format useful for guiding the verification effort.