Title :
Circuit reliability simulation based on Verilog-A
Author_Institution :
NXP Semicond., Eindhoven
Abstract :
An iterative simulation environment for reliability problems due to long-term circuit degradation has been developed for use in SPICE-like simulators. A model developed for the NBTI (negative bias temperature instability) degradation effect in the standard Verilog-A language can be used with this reliability simulator. Integration in a design environment allows easy access to reliability simulation for the circuit designer.
Keywords :
CMOS integrated circuits; SPICE; circuit reliability; circuit simulation; hardware description languages; integrated circuit design; SPICE-like simulator; Verilog-A language; circuit reliability simulation; negative bias temperature instability; Circuit simulation; Decision support systems; Hardware design languages;
Conference_Titel :
Behavioral Modeling and Simulation Workshop, 2007. BMAS 2007. IEEE International
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-1567-0
DOI :
10.1109/BMAS.2007.4437525
