A new BIST architecture: design and implementation in VLSI

Author

Sun, Xiaoling ; Olson, Michael ; Yeung, Daniel

Author_Institution

Dept. of Electr. Eng., Alberta Univ., Edmonton, Alta., Canada

fYear

1995

fDate

17-19 May 1995

Firstpage

457

Lastpage

460

Abstract

The paper describes a new built-in self-test (BIST) scheme for combinational circuitry. It employs signature analysis and Berger code for off-line BIST, and parity code for concurrent checking, with common testing circuitry. The logic design and VLSI implementation of the proposed scheme for a ROM is presented. The hardware cost and performance characteristics of the designed chip are discussed. The error detectability of the scheme is evaluated

Keywords

CMOS logic circuits; VLSI; built-in self test; codes; combinational circuits; design for testability; error detection; integrated circuit testing; logic design; logic testing; read-only storage; shift registers; BIST architecture; Berger code; ROM; VLSI; built-in self-test; combinational circuitry; concurrent checking; design; error detectability; hardware cost; implementation; logic design; parity code; performance characteristics; signature analysis; testing circuitry; Automatic testing; Built-in self-test; Circuit testing; Compaction; Costs; Design for testability; Logic design; Read only memory; System testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Computers, and Signal Processing, 1995. Proceedings., IEEE Pacific Rim Conference on

Conference_Location

Victoria, BC

Print_ISBN

0-7803-2553-2

Type

conf

DOI

10.1109/PACRIM.1995.519568

Filename

519568