DocumentCode
2852220
Title
Monolithic main memory
Author
Ayling, J. ; Moore, R.
Author_Institution
IBM Components Div., Hopewell Junction, NY, USA
Volume
XIV
fYear
1971
fDate
17-19 Feb. 1971
Firstpage
76
Lastpage
77
Abstract
A 128-bit bipolar memory chip with under 50-ns access delay at 0.5-mW per bit and with wide fabrication tolerances will be described. It is used for both main and control memory.
Keywords
Buffer storage; Decoding; Differential amplifiers; Driver circuits; Manufacturing processes; Preamplifiers; Pulse amplifiers; Switches; Switching circuits; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1971 IEEE International
Conference_Location
Philadelphia, PA, USA
Type
conf
DOI
10.1109/ISSCC.1971.1154984
Filename
1154984
Link To Document