DocumentCode
2852241
Title
A systematic approach to bit recursive systolic array design
Author
Liu, KuoJuey R. ; Yao, K.
Author_Institution
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
fYear
1988
fDate
25-27 May 1988
Firstpage
685
Lastpage
694
Abstract
This approach provides a systematic way to design a recursive computational architecture instead of a bit-slice architecture. Since the relationship is much stronger at the bit level than at the work level and most relations can be described as shift-and-operate computations, these kinds of relations can be formulated as recursive equations, from which the systolic array can be built without deriving the dependence graph of the bit-level computation. Some design examples for bit-recursive systolic array presented: multiplier, inner product and convolution correlation.<>
Keywords
VLSI; cellular arrays; recursive functions; bit recursive systolic array design; recursive computational architecture; recursive equations; Clocks; Computer architecture; Convolution; Design methodology; Digital signal processing; Equations; Filtering algorithms; Fourier transforms; Silicon; Systolic arrays;
fLanguage
English
Publisher
ieee
Conference_Titel
Systolic Arrays, 1988., Proceedings of the International Conference on
Conference_Location
San Diego, CA, USA
Print_ISBN
0-8186-8860-2
Type
conf
DOI
10.1109/ARRAYS.1988.18105
Filename
18105
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