Title :
Timing driven placement
Author :
Marek-Sadowska, M. ; Lin, S.P.
Author_Institution :
Electron. Res. Lab., California Univ., Berkeley, CA, USA
Abstract :
The authors address the problem of incorporating timing constraints into the physical design of integrated circuits. First they formulate the problem and discuss graph models suitable for its analysis. Next, they describe algorithms resulting in placements of improved performance in comparison to placements whose objective is to minimize the summation of wire lengths on the chip. Finally, the authors show preliminary results of their placement programs for the sea-of-gates designs.<>
Keywords :
circuit layout CAD; graph theory; logic CAD; algorithms; chip; graph models; improved performance; integrated circuits; minimize; physical design; placement programs; sea-of-gates designs; summation of wire lengths; timing constraints; timing driven placement; Conductors; Delay; Integrated circuit interconnections; Integrated circuit layout; Laboratories; Parasitic capacitance; Telephony; Timing; Very large scale integration; Wires;
Conference_Titel :
Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-1986-4
DOI :
10.1109/ICCAD.1989.76912
