First demonstration of drain current enhancement in SOI tunnel FET with vertical-tunnel-multiplication

Author

Morita, Yusuke ; Mori, Takayoshi ; Migita, S. ; Mizubayashi, W. ; Tanabe, A. ; Fukuda, Kenji ; Masahara, M. ; Ota, Hiroyuki

Author_Institution

Green Nanoelectron. Center (GNC), Nat. Inst. of Adv. Ind. Sci. & Technol. (AIST), Tsukuba, Japan

fYear

2012

fDate

1-4 Oct. 2012

Firstpage

1

Lastpage

2

Abstract

CMOS tunnel FETs (TFETs) with vertical-tunnel-multiplication (VTM) were fabricated. VTM TFETs initiate band-to-band tunneling (BTBT) parallel to the gate electric field and effectively extend the tunnel area. Impact of the VTM was analyzed using a distributed-element circuit model, and the drain current multiplication by extended tunnel area was experimentally revealed for the first time.

Keywords

CMOS integrated circuits; MOSFET; silicon-on-insulator; tunnel transistors; BTBT; SOI tunnel FET; TFET; VTM; band-to-band tunneling; distributed-element circuit model; drain current enhancement demonstration; drain current multiplication; gate electric field; vertical-tunnel-multiplication; Analytical models; CMOS integrated circuits; High K dielectric materials; Integrated circuit modeling; Logic gates; Numerical models; Resistance;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference (SOI), 2012 IEEE International

Conference_Location

NAPA, CA

ISSN

1078-621X

Print_ISBN

978-1-4673-2690-2

Electronic_ISBN

1078-621X

Type

conf

DOI

10.1109/SOI.2012.6404355

Filename

6404355