Title :
Block and track method for automated layout generation of MOS-LSI arrays
Author :
Kozawa, T. ; Horino, H. ; Watanabe, K. ; Nagata, M. ; Hukuda, H.
Author_Institution :
Hitachi, Ltd., Tokyo, Japan
Abstract :
An automated layout program with a block and track concept will be described. The program, which takes logic descriptions, can generate composite-patterns for single-chip calculator MOS-LSI arrays within 600 seconds computing time with manual-comparable chip areas.
Keywords :
Automatic logic units; Calculators; Equations; Humans; Integrated circuit interconnections; Large scale integration; Logic arrays; Logic circuits; Logic design; Wiring;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1972 IEEE International
Conference_Location :
Philadelphia, PA, USA
DOI :
10.1109/ISSCC.1972.1155010
