• DocumentCode
    2852747
  • Title

    Redefining and testing interconnect faults in Mesh NoCs

  • Author

    Cota, E. ; Kastensmidt, F.L. ; Cassel, M. ; Meirelles, P. ; Amory, A. ; Lubaszewski, M.

  • Author_Institution
    PPGC-Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre
  • fYear
    2007
  • fDate
    21-26 Oct. 2007
  • Firstpage
    1
  • Lastpage
    10
  • Abstract
    An extended fault model and novel strategy to tackle interconnect faults in network-on-chips are proposed. Short faults between distinct channels are considered in a cost-effective test sequence for mesh NoC topologies based on XY routing.
  • Keywords
    circuit reliability; fault diagnosis; integrated circuit testing; network-on-chip; cost-effective test sequence; mesh NoC; network-on-chips; redefining interconnect faults; testing interconnect faults; Circuit faults; Circuit testing; Crosstalk; Fault detection; Integrated circuit interconnections; Network-on-a-chip; Power system interconnection; Routing; Switches; System testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 2007. ITC 2007. IEEE International
  • Conference_Location
    Santa Clara, CA
  • ISSN
    1089-3539
  • Print_ISBN
    978-1-4244-1127-6
  • Type

    conf

  • DOI
    10.1109/TEST.2007.4437574
  • Filename
    4437574
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2852747