DocumentCode
2852762
Title
Testing hyperactive faults in asynchronous circuits
Author
Lioy, A. ; Maino, F. ; Odasso, G. ; Poncino, M.
Author_Institution
Dip. Automatica e Inf., Torino Univ., Italy
fYear
1995
fDate
17-19 May 1995
Firstpage
473
Lastpage
476
Abstract
Testing asynchronous circuits is a difficult task, because of two main reasons; first, the absence of a global clock does not allow the use of traditional test generation techniques used for synchronous circuits. Second, correct (i.e, hazard-free) operations of asynchronous circuits an usually obtained by introducing redundancies, that is, sacrificing the testability. The authors present an efficient test generator for asynchronous circuits which is based on a concurrent fault simulator. They also present an extension of the simulator which provides higher fault coverage by taking into consideration the detection of a special class of faults called hyperactive faults. Experimental results on a set of benchmarks has shown the effectiveness of the test generator, and proved that real circuits actually contain instances of such faults
Keywords
CMOS logic circuits; VLSI; asynchronous circuits; circuit analysis computing; digital simulation; fault diagnosis; integrated circuit testing; logic testing; asynchronous circuits; benchmarks; concurrent fault simulator; hyperactive faults; test generator; Asynchronous circuits; Benchmark testing; Circuit faults; Circuit simulation; Circuit testing; Clocks; Electrical fault detection; Fault detection; Redundancy; Synchronous generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications, Computers, and Signal Processing, 1995. Proceedings., IEEE Pacific Rim Conference on
Conference_Location
Victoria, BC
Print_ISBN
0-7803-2553-2
Type
conf
DOI
10.1109/PACRIM.1995.519572
Filename
519572
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