A vertical JFET with improved on to off current performance

This paper presents a vertical silicon-on-insulator enhancement mode junction field effect transistor (SOI JFET) for a better on to off current performance. A major problem limiting the scaling of bulk silicon CMOS is the diminished improvement in on current and the increase in off current. The short channel effects associated with MOSFET are a serious limitation for the scaling. The main problem of decreased on to off current performance can be overcome by using a SOI JFET. Here a 20nm SOI JFET (in 2D) has been analyzed using MEDICI^® (a Synopsis^® 2D-device simulation tool).