Efficient power droop aware delay fault testing

In today´s deep sub-micron designs, large amounts of switching activity may cause a substantial voltage drop on the power rails, also called power droop. Faults that may result from a power droop include delay faults caused by the increased propagation delays from the reduced supply voltage. In order to assess the performance of a manufactured chip, its worst-case droop condition should be tested by applying a specific input pattern which can cause maximum switching activity. On the contrary, during delay fault diagnosis, it would be beneficial for the diagnostic patterns to induce less switching activity in order to filter the embedded noise. In this paper, we propose a new SAT formulation that incorporates depth-limited search to compute the test patterns for these power droop faults. Experimental results demonstrate the efficiency of the proposed approach for generating test patterns for both transition and path-delay faults that also produce maximal (or minimal) power. Up to three orders of magnitude speed-up can be achieved using our approach.