Title :
Efficient power droop aware delay fault testing
Author :
Li, Bin ; Fang, Lei ; Hsiao, Michael S.
Author_Institution :
Dept. of Electr. & Comput. Eng.,, Virginia Tech., Blacksburg, VA
Abstract :
In today´s deep sub-micron designs, large amounts of switching activity may cause a substantial voltage drop on the power rails, also called power droop. Faults that may result from a power droop include delay faults caused by the increased propagation delays from the reduced supply voltage. In order to assess the performance of a manufactured chip, its worst-case droop condition should be tested by applying a specific input pattern which can cause maximum switching activity. On the contrary, during delay fault diagnosis, it would be beneficial for the diagnostic patterns to induce less switching activity in order to filter the embedded noise. In this paper, we propose a new SAT formulation that incorporates depth-limited search to compute the test patterns for these power droop faults. Experimental results demonstrate the efficiency of the proposed approach for generating test patterns for both transition and path-delay faults that also produce maximal (or minimal) power. Up to three orders of magnitude speed-up can be achieved using our approach.
Keywords :
automatic test pattern generation; delays; fault diagnosis; integrated circuit testing; ATPG; SAT formulation; deep sub-micron designs; delay fault diagnosis; maximal power; maximum switching activity; power droop aware delay fault testing; power rails; propagation delays; switching activity; test patterns generation; voltage drop; Circuit faults; Circuit testing; Delay effects; Fault diagnosis; Filters; Propagation delay; Rails; Switching circuits; Test pattern generators; Voltage;
Conference_Titel :
Test Conference, 2007. ITC 2007. IEEE International
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4244-1127-6
Electronic_ISBN :
1089-3539
DOI :
10.1109/TEST.2007.4437597