Testing for systematic defects based on DFM guidelines

With shrinking feature sizes of manufacturing processes, the occurrence of systematic defects is expected to increase. In this paper, we present techniques for identifying potential systematic defect candidates from design-for-manufacturing (DFM) layout guidelines. DFM guidelines are tightened to find layout locations as potential sites for systematic defects, affected transistors are identified at the schematic level, and defect behaviors are translated to gate level logic faults. Experimental results are (R) presented on an Intel Pentium^reg 4 design for the evaluation of existing tests in screening systematic failures and identifying potential test holes. Additional test content is generated for improving test quality.