• DocumentCode
    2853164
  • Title

    SOI tri-gate nanowire MOSFETs for ultra-low power LSI

  • Author

    Saitoh, Masatoshi ; Ota, Kaoru ; Tanaka, C. ; Uchida, Kazunori ; Numata, T.

  • Author_Institution
    Adv. LSI Technol. Lab., Toshiba Corp., Yokohama, Japan
  • fYear
    2012
  • fDate
    1-4 Oct. 2012
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    We demonstrated high-Ion and small-σVth 10nm-NW Tr. wth SMT. Tri-gate NW structures with small HNW and thin BOX offer high Vth tunability by Vsub. SOI tri-gate NW Tr. presented in this work is a key device in future ultralow-power CMOS LSI.
  • Keywords
    CMOS integrated circuits; MOSFET; large scale integration; low-power electronics; nanoelectronics; nanowires; silicon-on-insulator; SMT; SOI trigate NW Tr; SOI trigate nanowire MOSFET; nanowire transistors; size 10 nm; small HNW; thin BOX; trigate NW structures; ultralow-power CMOS LSI; CMOS integrated circuits; Delay; Grain boundaries; Large scale integration; Logic gates; Power demand; Strain;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference (SOI), 2012 IEEE International
  • Conference_Location
    NAPA, CA
  • ISSN
    1078-621X
  • Print_ISBN
    978-1-4673-2690-2
  • Electronic_ISBN
    1078-621X
  • Type

    conf

  • DOI
    10.1109/SOI.2012.6404396
  • Filename
    6404396
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2853164