Title :
A 4096-bit dynamic MOS RAM
Author :
Karp, Jann ; Regitz, W. ; Chou, Sheng
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
A memory employing a 3-transistor cell 2 mil2in area will be described. Access and cycle times are under 300 ns and 500 ns, respectively, at 100 μW/bit dissipation; standby power is 1 μW/bit. All inputs except the single clock are TTL compatible.
Keywords :
Clocks; Emergency power supplies; MOSFETs; Packaging; Pulsed power supplies; Random access memory; Read-write memory; Timing; Voltage; Writing;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1972 IEEE International
Conference_Location :
Philadelphia, PA, USA
DOI :
10.1109/ISSCC.1972.1155044
