Achieving high transition delay fault coverage with partial DTSFF scan chains

The delay test scan flip-flop (DTSFF) has been recently presented as a low cost DFT technique to achieve both launch-on-shift (LOS) and launch-on-capture (LOC) scan delay tests, without the need for a fast scan enable signal. Such a combined delay test strategy can achieve near perfect transition delay fault (TDF) coverage which eludes commonly supported LOC only delay tests. In this paper we show that a partial DTSFF scheme, which replaces only 20-40% carefully chosen scan flip-flops in the scan chain with the new DTSFF can achieve most of the coverage benefits of a full DTSFF design while minimizing area overhead.