Enhancing signal controllability in functional test-benches through automatic constraint extraction

Functional test-bench development is a tedious and time-consuming process that requires tremendous engineering effort. Developing proper test-benches is crucial for both functional verification and post-silicon performance validation. Constrained random test generation is a popular approach to alleviate the burden of test-bench development. This paper presents an automatic constraint extraction tool that can be easily integrated with an existing commercial constrained random test generation framework. This tool extracts constraints by analyzing test-bench simulation data. These constraints, when added into a test-bench, can provide controllability of signals that are deeply embedded in a complex design. We develop simulation data mining algorithms for constraint extraction and demonstrate the effectiveness of our approach based on OpenSparc Tl microprocessor.