High-level synthesis of fault-tolerant ASICs

Author

Karri, Ramesh ; Orailoglu, A.

Author_Institution

Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA

Volume

1

fYear

1992

fDate

10-13 May 1992

Firstpage

419

Abstract

Methodologies for the high-level synthesis of fault-tolerant application-specific ICs (ASICs) that maximize performance in the presence of fault-tolerance and cost constraints are developed. The fault-tolerance constraints supported include number of faults per module (fault-masking constraint) and chip reliability (reliability constraint). Experience with the system shows that (a) it is feasible to automate design for fault-tolerance and (b) controlled interplay between cost, performance, and fault-tolerance, during high-level synthesis, helps synthesize high-quality and cost-effective fault-tolerant ASICs

Keywords

VLSI; application specific integrated circuits; circuit CAD; circuit reliability; chip reliability; cost constraints; fault-masking constraint; fault-tolerant ASICs; high-level synthesis; Algorithm design and analysis; Application specific integrated circuits; Circuit faults; Costs; Fault tolerance; Fault tolerant systems; High level synthesis; Integrated circuit reliability; Redundancy; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0593-0

Type

conf

DOI

10.1109/ISCAS.1992.229924

Filename

229924