Title :
Fault equivalence analysis and reduction of two level test set for multilevel logic synthesis
Author :
Hsu, Wen-Jun ; Shen, Wen-Zen ; Shyu, Jyuo-Min
Author_Institution :
Nat. Chiao Tung Univ., Hsin-Chu, Taiwan
Abstract :
The relationship between faults in a synthesized multilevel network and in its collapsed two-level network is analyzed. A program to select a proper set of faults in the collapsed two-level network from the synthesized multilevel network is implemented. The test for selected faults will detect all single stuck-at faults of the synthesized multilevel network. The number of generated tests is about 50% less than the number for the two-level complete test set
Keywords :
fault location; logic design; logic testing; many-valued logics; collapsed two-level network; fault equivalence analysis; logic testing; multilevel logic synthesis; selected faults; stuck-at faults; two level test set; Circuit faults; Circuit synthesis; Circuit testing; Design for testability; Electrical fault detection; Electronic equipment testing; Fault detection; Logic design; Logic testing; Network synthesis;
Conference_Titel :
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0593-0
DOI :
10.1109/ISCAS.1992.229925
