DocumentCode
285339
Title
A BIST methodology for iterative logic arrays
Author
Su, Chauchin ; Lemke, John K. ; Chen, Minbo ; Kime, Charles R.
Author_Institution
Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
Volume
1
fYear
1992
fDate
10-13 May 1992
Firstpage
411
Abstract
A methodology for pseudoexhaustive test of unilateral, one-dimensional iterative logic arrays (ILAs) in a built-in self-test environment is presented. Exhaustive patterns applied over a test frame permit application of exhaustive patterns to a cell and observation of its outputs. A test frame is composed of an initializing subframe. The pseudoexhaustive test design is performed by an algorithm that simply determines the length of the test frame. Algorithm results are given and a design-for-testability technique for ILAs is discussed
Keywords
built-in self test; design for testability; logic arrays; logic testing; BIST methodology; ILAs; design-for-testability technique; initializing subframe; iterative logic arrays; pseudoexhaustive test; test frame; Built-in self-test; Circuit testing; Design for testability; Electrical fault detection; Fault detection; Hardware; Iterative methods; Logic arrays; Test pattern generators; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Conference_Location
San Diego, CA
Print_ISBN
0-7803-0593-0
Type
conf
DOI
10.1109/ISCAS.1992.229926
Filename
229926
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