Probability, graphs, electrical networks and computer fault diagnosis

A method for the identification of faulty interprocessor links in an arbitrarily large multiprocessor assembly is described. The description given and the associated examples refer to the single fault case, but the procedure is readily adapted to multiple faults and to processor (vertex) fault diagnosis. The diagnostic process is probabilistic and compares a sequence of faulty computational substructures which may be, as used here, computational trees in the graph of the system. The various probabilities used in the analysis are obtainable numerically as electrical resistance values in a resistor network having the same structure as the system graph