Title :
A three transistor MOS memory cell with internal refresh
Author :
Walther, Thomas ; McCoy, Michael B.
Author_Institution :
Electronic Arrays, Inc., Mountain View, Cal., USA
Abstract :
A 1024-bit N-channel read/write memory has been fabricated using a memory call composed of three minimum geometry transistors. Each cell includes refresh circuitry within its 6.7 mil2area.
Keywords :
Capacitance; Circuits; Hardware; Large-scale systems; Logic arrays; Logic devices; MOS capacitors; MOSFETs; Read-write memory; Threshold voltage;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1972 IEEE International
Conference_Location :
Philadelphia, PA, USA
DOI :
10.1109/ISSCC.1972.1155062
