• DocumentCode
    285346
  • Title

    Improved techniques for multiple stuck-at fault analysis using single stuck-at fault test sets

  • Author

    Camurati, P. ; Prinetto, P. ; Rebaudengo, M. ; Reorda, M. Sonza

  • Author_Institution
    Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
  • Volume
    1
  • fYear
    1992
  • fDate
    10-13 May 1992
  • Firstpage
    383
  • Abstract
    Previous studies have suggested that many multiple stuck-at faults are detected by the test patterns generated to detect single stuck-at faults, but a fault simulation is often impossible, as their number grows and becomes enormous as real-sized circuits are considered. Thus, rules are needed to decrease their number by neglecting those that are surely detected by the patterns generated for single stuck-ats. A procedure is first given for establishing whether a multiple stuck-at fault is detected by a pattern. Then this procedure is used to prove a set of rules that allows the size of the fault list to be decreased significantly. Experimental results on the standard set of combinational benchmark circuits are provided, showing the effectiveness of the approach
  • Keywords
    automatic testing; combinatorial circuits; fault location; integrated logic circuits; logic testing; combinational benchmark circuits; fault list; fault simulation; multiple stuck-at fault analysis; real-sized circuits; single stuck-at fault test sets; test patterns; Automatic testing; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Electrical fault detection; Fault detection; Gold; Sufficient conditions; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
  • Conference_Location
    San Diego, CA
  • Print_ISBN
    0-7803-0593-0
  • Type

    conf

  • DOI
    10.1109/ISCAS.1992.229933
  • Filename
    229933