VLSI design and implementation of a self-testing systolic array chip for signal processing

A CMOS VLSI implementation of a built-in self-test (BIST) systolic array that can perform both self-test and self-diagnosis is presented. The BIST is combined with a scan path design; therefore, all registers in the array cells are connected as a scan chain and all signatures are shifted out by this scan chain to be compared with a previously generated fault-free signature. Thus, the signature generated by the BIST circuitry determines the status of each cell. The cell is partitioned so that the resulting combinational networks can be cycled through all possible input combinations in the time allowed for testing. Therefore, no fault models or test pattern generation program are required. Various signal processing algorithms, such as multiplication, the FFT, and convolution, can be efficiently performed by an array of these BIST cells