Fast and effective fault simulation for path delay faults based on selected testable paths

Test generation and fault simulation of path delay faults are very time-consuming. A new fault simulation method of fully enhanced scan designed circuits is proposed for path delay faults based on single stuck-at tests without circuit transformation. The proposed method identifies robustly and non-robustly testable paths first, for which a selected path circuit (SPC) is constructed. The SPC circuit contains no internal fanouts. Fault simulation of non-robustly testable paths is reduced to 3-valued logic simulation of the SPC circuit. Fault simulation is completed on the SPC circuit by only tracing the active part of SPC circuit. An effective fault dropping technique is also adopted based on the selective tracing scheme. The proposed fault simulation scheme is extended to that of robustly testable path delay faults. Experimental results confirm that the proposed fault simulator is exact. It is shown according to experimental results that the proposed fault simulator gets exact fault simulation results in very short time. Sufficient experimental results are presented to compare with previous methods on CPU time and accuracy.