Title :
On the computation of the ranges of detected delay fault sizes
Author :
Pramanick, Ankan K. ; Reddy, Sudhakar M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., IA, USA
Abstract :
Existing methodologies for determining gate delay fault coverages through the computation of detected fault sizes are shown to have certain deficiencies. A method is proposed to determine all the possible ranges of detected fault sizes, thereby maximizing the fault coverage of a given test sequence. The ultimate goal of ensuring that the coverage for a particular fault extends up to the actual circuit slack is explored, and methods are given to achieve such coverages wherever possible. Results of experiments performed to evaluate the practical benefits of the proposed methods are reported.<>
Keywords :
automatic testing; delays; electronic engineering computing; fault location; logic gates; logic testing; automatic testing; circuit slack; fault coverage; fault detection; fault sizes; gate delay fault; logic testing; Circuit faults; Circuit testing; Cities and towns; Clocks; Contracts; Delay; Electrical fault detection; Fault detection; Logic circuits; Performance evaluation;
Conference_Titel :
Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-1986-4
DOI :
10.1109/ICCAD.1989.76919
