Data compression at low power using soft competitive learning

This paper examines a variety of issues relating to the analog hardware implementation of the soft competitive neural learning algorithm and its suitability for use in data compression applications. Specifically, we investigate the impact of realizing the theoretical learning algorithm in imperfect analog structures constructed in a traditional CMOS fabrication process. Empirical measurements of previously fabricated neural circuit elements are used to produce suitable hardware models which accurately characterize the fabrication process and a typical operating environment. These models are used to evaluate the tolerance of the soft competitive learning algorithm to expected system variations including various noise and device effects. The analog neural circuits make extensive use of a CMOS implementation of the Gilbert multiplier which is the primary computational element for our learning computations. We have found, through the aid of simulations based on these hardware models, that the circuit effects are not significant if zero-thresholding is used to compensate for multiplier zero-crossing offsets. These results indicate that this algorithm is very robust in the presence of moderate circuit limitations. As a result, such circuits would be well suited for applications requiring data compression with low power consumption, as might be encountered in the production of compact consumer products for portable computing