DocumentCode
285388
Title
Scheduling real-time recursive DSP algorithms with fixed interprocessor communication delays
Author
Hu, Yu Hen ; Wang, Duen-Jeng
Author_Institution
Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
Volume
1
fYear
1992
fDate
10-13 May 1992
Firstpage
180
Abstract
The problem of multiprocessor implementation of real-time recursive DSP algorithms with fixed interprocessor communication delay is studied. A strategy to achieve the objective is presented. An efficient heuristic algorithm for finding a rate-optimal schedule, given the processor allocation, is introduced
Keywords
digital signal processing chips; multiprocessor interconnection networks; parallel algorithms; real-time systems; scheduling; fixed interprocessor communication delays; heuristic algorithm; multiprocessor implementation; processor allocation; rate-optimal schedule; real-time recursive DSP algorithms; Delay; Digital filters; Digital signal processing; IIR filters; Multiprocessing systems; Nonlinear filters; Parallel processing; Processor scheduling; Scheduling algorithm; Signal processing algorithms;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Conference_Location
San Diego, CA
Print_ISBN
0-7803-0593-0
Type
conf
DOI
10.1109/ISCAS.1992.229984
Filename
229984
Link To Document