Parallel architectures for 8×8 discrete cosine transforms

Author

Wolter, S. ; Birreck, D. ; Heine, M. ; Laur, R.

Author_Institution

Inst. fuer Microelektron, Bremen Univ., Germany

Volume

1

fYear

1992

fDate

10-13 May 1992

Firstpage

149

Abstract

The design of multiplier-free parallel architectures for computing the 8×8 discrete cosine transform (DCT) is addressed. The focus is on direct methods, which avoid a row-column decomposition. Two architectures are proposed and compared. One uses polynomial transforms; the other computes the DCT via the Walsh-Hadamard transform (WHT). Both architectures achieve a high degree of parallelism and regularity. The architectures are designed for HDTV sampling rates and can be efficiently realized in CMOS technology

Keywords

CMOS integrated circuits; discrete cosine transforms; parallel architectures; 8×8 DCT; CMOS technology; DCT computation; HDTV sampling rates; WHT; Walsh-Hadamard transform; degree of parallelism; direct methods; discrete cosine transforms; hardware; multiplier-free parallel architectures; polynomial transforms; regularity; CMOS technology; Computer architecture; Concurrent computing; Discrete cosine transforms; Discrete transforms; HDTV; Parallel architectures; Parallel processing; Polynomials; Sampling methods;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0593-0

Type

conf

DOI

10.1109/ISCAS.1992.229992

Filename

229992