Title :
Design-for-reliability: A soft error case study
Author_Institution :
Intel Corp., Folsom, CA
Abstract :
The purpose of this lecture is to illustrate a design-for-reliability (DFR) strategy via a soft error case study. We review relevant methodologies that target different levels and stages of a multi-core design: soft error modeling, robust circuit design, microarchitecture, and chip architecture. Finally we discuss several emerging DFR challenges and possible mitigation solutions.
Keywords :
VLSI; integrated circuit design; integrated circuit reliability; radiation hardening (electronics); VLSI; chip architecture; design-for-reliability; microarchitecture; multi-core design; robust circuit design; soft error case study; soft error modeling; Circuit synthesis; Circuit testing; Error analysis; Error correction codes; Flip-flops; Logic circuits; Microarchitecture; Protection; Robustness; Very large scale integration;
Conference_Titel :
Test Conference, 2007. ITC 2007. IEEE International
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4244-1127-6
Electronic_ISBN :
1089-3539
DOI :
10.1109/TEST.2007.4437664
