Abstract :
For almost two decades, at-speed scan tests have been actively pursued as a manufacturing test methodology in industry, and as an active field of research in academia. However, there is continued debate on the value and applicability of at-speed scan tests, specifically whether they will enable us to replace or significantly mitigate the need for at-speed functional tests. Numerous barriers still exist in the realization of this goal. The primary contributors to this barrier are design constraints (logical, timing and electrical) and the lack of comprehensive quality metrics beyond gross transition/path delay fault coverage. Besides the applicability of scan at-speed tests in screening subtle speed-dependent manufacturing defects, it is not clear if such tests have the resolution to address speed binning. Till such barriers to adoption of at-speed scan are lowered or overcome, at-speed scan as a universally applicable push-button methodology for comprehensive delay testing will remain a fantasy.
Keywords :
delays; fault diagnosis; integrated circuit manufacture; production testing; at-speed functional tests; at-speed scan tests; gross transition delay fault coverage; manufacturing test methodology; path delay fault coverage; push-button methodology; quality metrics; Process variations; atspeed test; functional test; small delay defects; structural (scan) test; test debug; test quality; timing analysis; timing exceptions and constraints; yield loss;
