At-speed scan tests are a reality (and a necessity)

Some defects in today´s vanishingly tiny IC process geometries are manifested as delay faults which are best detected by test patterns that contain launch and capture events applied at-speed. While functional tests may meet this criterion, creation of functional tests for specifically targeted delay faults is very problematic. There is no general systematic method to create sufficiently comprehensive functional patterns on a realistic schedule such that project completion is assured by a specific date. A far more reliable strategy is to use scan-based delay tests. AMD is ever more heavily invested in scan-based methods. We have a very capable at-speed scan architecture that we use to test the great majority of the logic circuitry that operates synchronously at GHz frequencies.