Statistical analysis of timing rules for high-speed synchronous interconnects

A statistical model which takes both static timing skew and random timing skew into account for deriving the timing rules of synchronous VLSI systems is proposed and analyzed. Based on this model, the relationship between the maximum system throughput and the timing skew (both static and random) for a synchronous system is derived. Two timing schemes are evaluated for each of the system configurations. In the first, the transmitter cannot initiate the next cycle until the receiver has received the data. In the second, the transmitter initiates the next cycle as soon as the current data have been sent out. From this timing skew model it is shown that the risetime of the clock as well as the data is critical in determining the performance of synchronous interconnections