ITC 2007 panel session the new ATE: Protocol aware

Silicon Companies with substantial IP libraries can tape out and manufacture a device that is a true "system" with diverse IP blocks in a single process on a single die. It is an ever increasing difficulty to adequately and cost effectively test a device at a "system level", let alone implement DFT for a "system" vs. a multitude of stand-alone IP islands, each with their own test strategy often with orthogonal test stimulus requirements. In the past 20 years, since the first mixed-signal or SOC ATE test systems appeared, there has not been any significant evolution in ATE architecture allowing for true system level test. This panel will take a 360 degree approach to explore the possibilities of protocol aware (PA) ATE and integration of today\´s test flows and methodologies. The PA ATE architecture is an enabler for true system level testing as part of a production test flow and methodology. ATE will be transformed from a simulation based environment to also include a real time Protocol Aware environment which enables tremendous new capabilities and benefits. Protocol aware ATE is possible, and it is next level of ATE evolution required to achieve lowest possible defect rate (<100DPM), lowest cost, and fastest time to market for highly integrated semiconductors.