• DocumentCode
    2854631
  • Title

    An 8192-bit shift register

  • Author

    Harland, R.

  • Author_Institution
    Microsystems INternational, Ltd., Ottawa, Canada
  • Volume
    XVI
  • fYear
    1973
  • fDate
    14-16 Feb. 1973
  • Firstpage
    54
  • Lastpage
    55
  • Abstract
    A three-phase shift-register cell comprising six minimum geometry transistors per bit has been designed. Cell consuming less power and silicon area than comparable designs, permitted fabrication of 8192-bit shift register.
  • Keywords
    Buffer storage; Circuits; Clocks; Geometry; Parasitic capacitance; Random access memory; Read-write memory; Shift registers; Silicon; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1973 IEEE International
  • Conference_Location
    Philadelphia, PA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1973.1155130
  • Filename
    1155130
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2854631