Title :
An 8192-bit shift register
Author_Institution :
Microsystems INternational, Ltd., Ottawa, Canada
Abstract :
A three-phase shift-register cell comprising six minimum geometry transistors per bit has been designed. Cell consuming less power and silicon area than comparable designs, permitted fabrication of 8192-bit shift register.
Keywords :
Buffer storage; Circuits; Clocks; Geometry; Parasitic capacitance; Random access memory; Read-write memory; Shift registers; Silicon; Switches;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1973 IEEE International
Conference_Location :
Philadelphia, PA, USA
DOI :
10.1109/ISSCC.1973.1155130
