DocumentCode
2854865
Title
Optimal granularity of test generation in a distributed system
Author
Fujiwara, H. ; Inoue, T.
Author_Institution
Dept. of Comput. Sci., Meiji Univ., Kawasaki, Japan
fYear
1989
fDate
5-9 Nov. 1989
Firstpage
158
Lastpage
161
Abstract
The problem of test generation for logic circuits is known to be NP-hard, and hence it is very hard to speed up the test generation process due to its backtracking mechanism. The authors present an approach to parallel processing of test generation for logic circuits in a loosely coupled distributed network of general-purpose computers. They analyze the effects of the allocation of target faults to processors, the optimal granularity (grain size of target faults), and the speedup ratio of the multiple-processor system to a single-processor system. To analyze the case in which a test pattern generated for one fault can also be a test pattern for other faults if fault simulation is performed, they introduce a ratio of newly processed faults to target faults and derive the expressions of optimal granularity in cases of both static and dynamic task allocation. They also derive an expression of the speedup of a multiple-processor system in the homogeneous case. The analysis indicates that the speedup approaches N, the number of servers, if the data transfer time per fault and the waiting time per communication are much smaller than the processing time per fault and if the decrease ratio of newly processed faults due to overlapped processing is much smaller than the ratio of newly processed faults.<>
Keywords
automatic testing; electronic engineering computing; fault location; integrated logic circuits; logic testing; parallel processing; allocation of target faults; backtracking; data transfer time; distributed system; dynamic task allocation; fault simulation; logic circuits; multiple-processor system; optimal granularity; overlapped processing; parallel processing; processing time; static task allocation; target faults; test generation; test pattern; waiting time; Circuit faults; Circuit testing; Computer networks; Concurrent computing; Coupling circuits; Distributed computing; Logic circuits; Logic testing; Parallel processing; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on
Conference_Location
Santa Clara, CA, USA
Print_ISBN
0-8186-1986-4
Type
conf
DOI
10.1109/ICCAD.1989.76926
Filename
76926
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