Uninterpreted modeling using the VHSIC hardware description language (VHDL)

The authors discuss methodologies and tools that allow a system to be analyzed using Petri nets or queuing models. Models at this level contain tokens rather than values, and the function of blocks remains undefined. Such analysis is performed early in the design process to evaluate overall system performance. Different methodologies and tools are available to allow design analysis and verification at interpreted levels through hardware design language (HDL) descriptions. Tokens are replaced with specific values for the representation of signals. The methodology presented allows the designer to create uninterpreted models in an environment already capable of interpreted modeling, the VHSIC hardware description language (VHDL). Uninterpreted modeling in an HDL is the first step in the creation of a continuous single-path design environment.<>