An efficient method for parametric yield optimization of MOS integrated circuits

A method for parametric yield optimization which significantly reduces the simulation cost is proposed. The method assumes that the circuit performances ultimately determining yield can be approximated by computationally inexpensive functions of the inputs to the circuit simulator. These inputs are the designable parameters, the uncontrollable statistical variations, and the operating conditions of interest. The authors fit the approximating functions to data from a statistical experiment incurring relatively few runs of the simulator. For a given set of designable parameters, the fitted models predict the circuit performances as the uncontrollable parameters and operating conditions vary. The predictions lead to estimates of the parametric yield, which is then numerically maximized with respect to the designable parameters. The authors give a CMOS circuit example where sufficiently accurate predictions and good actual yield result from about 100 runs of the circuit simulator.<>