Title :
State assignment for initializable synthesis (gate level analysis)
Author :
Cheng, K.-T. ; Agrawal, V.D.
Author_Institution :
AT&T Bell Lab., Murray Hill, NJ, USA
Abstract :
Proper consideration of initializability during state assignment can guarantee success for gate level analysis tools. The necessary and sufficient conditions for initializability are derived. The new state assignment algorithm uses additional constraints for initialization by a preselected input sequence. Experimental results show that, in most cases, this method does not require more hardware than the other methods that may produce an uninitializable design. A partial reset technique is suggested for machines without a synchronizing sequence.<>
Keywords :
logic CAD; logic testing; CAD; constraints; gate level analysis tools; initializable synthesis; logic testing; partial reset technique; preselected input sequence; state assignment; Automata; Circuit simulation; Circuit synthesis; Circuit testing; Logic testing; Minimization; Sequential analysis; Sequential circuits; Sufficient conditions; System testing;
Conference_Titel :
Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-1986-4
DOI :
10.1109/ICCAD.1989.76938
